XSPICE includes a library of predefined "Code Models" that can be placed within any circuit description in a manner similar to that used to place standard SPICE device models. Code model instance cards always begin with letter "A", and always make use of a .MODEL card to describe the code model desired.

The Code model instance is:

A<name> <input ports> <output ports> <model name>

Note

Note that, by convention, input ports are specified first on code models. Output ports follow the inputs.

Node Connections

The expected node order for each code model instance call line can be found in the Port Table which are given for each device in the Code Model description. The Port table describes the types of inputs that can be used to drive the device and the default input type.

Code models can have any combination of three different types of nodal connections; single-ended (ground referenced), differential, or vector. A single-ended node consists of a normal SPICE node designation. A differential node is specified by grouping two nodes in parentheses, such as;

a (1 2) 3 limit1

The parentheses indicate that the input to the element is a differential signal V(1)-V(2). Vector nodes are a bus type connection and are normally used on digital code models. For example, there is only one Nand code model, but it supports a vector type input. This allows the model to simulate any input configuration, for example, a 3-input Nand gate.

Anand [1 2 3] 4 nand3

Node Modifiers

The types of inputs that can be used for a particular code model are specified in the model’s Port Table. The default port type entry specifies the type of input signal expected if no port modifier is present. To use an alternate type of input, one of the modifiers listed in the following Port Modifiers table can be inserted preceding the node number.

Note Note: The alternate input must still be one of the types listed in the “allowed types” entry of the Port table.

The optional symbols %v, %i, %vd, etc. specify the type of port the simulator is to expect for the subsequent port or port vector. The meaning of each symbol is given in following table.

Modifier	Description
%v	Represents a single-ended voltage port. One node name is expected for each port.
%i	Represents a single-ended current port. One node name is expected for each port.
%g	Represents a single-ended voltage-input, current-output (VCCS) port. One node name is expected for each port. This type of port is automatically an input/output.
%h	Represents a single-ended current-input, voltage-output (CCVS) port. One node name is expected for each port. This type of port is automatically an input/output.
%d	Represents a digital port. One node name is expected for each port. This type of port may be either an input or an output.
%vnam	Represents the name of a voltage source, the current through which is taken as an input.
%vd	Represents a differential voltage port. Two node names are expected for each port.
%id	Represents a differential current port. Two node names are expected for each port.
%gd	Represents a differential VCCS port. Two node names are expected for each port.
%hd	Represents a differential CCVS port. Two node names are expected for each port.

The symbols described may be omitted if the default port type for the model is desired. Note that non-default port types for multi-input or multi-output (vector) ports must be specified by placing one of the symbols in front of each vector port. On the other hand, if all ports of a vector port are to be declared as having the same non-default type, then a symbol may be specified immediately prior to the opening bracket of the vector. the following examples should make this clear:

%vd [1 2 3 4]

Specifies two differential voltage connections, one to nodes 1 & 2, and one to nodes 3 & 4.

%v [1 2 %vd 3 4]

Specifies two single-ended connections to node 1 and at node 2, and one differential connection to nodes 3 & 4.

%v [1 2 %vd(3 4)]

Identical to the previous example. Parenthesis are added for additional clarity.

[1 2 3 4]

Specifies that the node numbers are to be treated in the default fashion for the particular model. Is this model had %v as a default for this port, then this notation would represent four single-ended voltage connections.

A2 1 %id(2 3) Table

Normally the Table model uses a voltage input and a voltage output. Using this syntax the table model would take an input voltage at node 1 and output the current between nodes 2 to 3.

A2 %vnam(VCC) %vd(2 3) Limiter

Normally the limiter model uses a voltage input and a voltage output. Using this syntax, the limiter model would take the current flowing through the source named VCC and output a differential voltage across nodes 2 to 3.

Square brackets

Square brackets are used to enclose vector input nodes.

NULL Connections

The literal string null, when included in a node list, is interpreted as no connection at that input to the model. Null is only allowed if the Null_Allowed value in the Port Table is “yes”. Null is not allowed as the name of a model's input or output if the model only has one input or one output.

Inverting Digital Nodes

The tilde, "~", when prepended to a digital node name, specifies that the logical value of that node must be inverted prior to being passed to the code model. The following example defines a NAND gate, one input of which is inverted:

a1 [~1 2] 3 nand1

Model name

Code model instance cards always make use of a .MODEL card to describe the code model desired; model name is the code model name. See XSPICE code model.

Examples

A1 1 2 AMP
.MODEL AMP GAIN(GAIN=5.0)

A2 [~1 2] 3 NAND1
.MODEL NAND1 D_NAND(RISE_DELAY=0.1 FALL_DELAY=0.2)


XSPICE devices