16-Bit Loadable Cascadable Binary Counter with Clock Enable and Synchronous Reset

CB16RLE is a 16-stage, 16-bit, synchronous, loadable, resettable, cascadable binary counter. The synchronous reset (R) is the highest priority input. The synchronous R, when High, overrides all other inputs and resets the Q15 – Q0, TC, and CEO outputs to Low on the Low-to-High clock (C) transition. The data on the D15 – D0 inputs is loaded into the counter when the load enable input (L) is High during the Low-to- High clock (C) transition, independent of the state of CE. The outputs (Q15 – Q0) increment when CE is High during the Low-to-High clock transition. The counter ignores clock transitions when CE is Low.

The TC output is High when all Q outputs are High. The CEO output is High when all Q outputs and CE are High, to allow direct cascading of counters. Larger counters are created by connecting the CEO output of the first stage to the CE input of the next stage and connecting the C, L, and R inputs in parallel. The maximum length of the counter is determined by the accumulated CE-to-CEO propagation delays versus the clock period.

When cascading counters, use the CEO output if the counter uses the CE input; use the TC output if it does not.

Parameters

Parameter Description Units Default
DELAY Propagation delay. s DGTDELAY
IN_MODE Inputs mode.   IN
OUT_MODE Outputs mode.   OUT
IOMODEL The name of an I/O model, which describes the device’s loading and driving characteristics.   DGTDEFIOMODEL
POWER_NODE Digital power node name. Is the node used by the interface subcircuits which connect analog nodes to digital nodes.   $G_DPWR
GROUND_NODE Digital ground node name. Is the node used by the interface subcircuits which connect analog nodes to digital nodes.   $G_DGND