4-Bit Loadable Cascadable Bidirectional Binary Counter with Clock Enable and Asynchronous Clear

CB4X1 is a 4-stage, 4-bit, synchronous, loadable, clearable, bidirectional binary counter. The asynchronous clear (CLR) is the highest priority input. When CLR is High, all other inputs are ignored, data outputs (Q3 – Q0) go to logic level zero, and terminal count outputs TCU and TCD go to zero and one, respectively, independent of clock transitions. The data on the D3 – D0 inputs loads into the counter on the Low-to-High clock (C) transition when the load enable input (L) is High, independent of the CE inputs.

The outputs (Q3 – Q0) increment when CEU is High, provided CLR and L are Low, during the Low-to-High clock transition. The outputs (Q3 – Q0) decrement when CED is High, provided CLR and L are Low. The counter ignores clock transitions when CEU and CED are Low. Both CEU and CED should not be High during the same clock transition; the CEOU and CEOD outputs might not function properly for cascading when CEU and CED are both High.

For counting up, the CEOU output is High when all Q outputs and CEU are High. For counting down, the CEOD output is High when all Q outputs are Low and CED is High. To cascade counters, the CEOU and CEOD outputs of each counter are connected directly to the CEU and CED inputs, respectively, of the next stage. The clock, L, and CLR inputs are connected in parallel.

When cascading counters, the final terminal count signals can be produced by AND-ing all the TCU outputs (for the up direction) and all the TCD outputs (for the down direction).

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