8-Bit Loadable Cascadable Bidirectional Binary Counter with Clock Enable and Synchronous Reset

CB8X2 is an 8-stage, 8-bit, synchronous, loadable, resettable, bidirectional binary counter. The synchronous reset (R) is the highest priority input. When R is High, all other inputs are ignored, data outputs (Q7 – Q0) go to logic level zero, and terminal count outputs TCU and TCD go to zero and one, respectively, on the Low-to-High clock (C) transition. The data on the D7 – D0 inputs loads into the counter on the Low-to-High clock (C) transition when the load enable input (L) is High, independent of the CE inputs.

The outputs (Q7 – Q0) increment when CEU is High, provided R and L are Low, during the Low-to-High clock transition. The outputs (Q7 – Q0) decrement when CED is High, provided R and L are Low. The counter ignores clock transitions when CEU and CED are Low. Both CEU and CED should not be High during the same clock transition; the CEOU and CEOD outputs might not function properly for cascading when CEU and CED are both High.

For counting up, the CEOU output is High when all Q outputs and CEU are High. For counting down, the CEOD output is High when all Q outputs are Low and CED is High. To cascade counters, the CEOU and CEOD outputs of each counter are connected directly to the CEU and CED inputs, respectively, of the next stage. The C, L, and R inputs are connected in parallel.

the maximum clocking frequency of these counter components is unaffected by the number of cascaded stages for all counting and loading functions. The TCU terminal count output is High when all Q outputs are High, regardless of CEU. The TCD output is High when all Q outputs are Low, regardless of CED.

When cascading counters, the final terminal count signals can be produced by AND-ing all the TCU outputs (for the up direction) and all the TCD outputs (for the down direction).

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