4-Bit Cascadable BCD Counter with Clock Enable and Asynchronous Clear

CD4CE is a 4-stage, 4-bit, synchronous, clearable, cascadable binarycoded- decimal (BCD) counter. The asynchronous clear input (CLR) is the highest priority input. When CLR is High, all other inputs are ignored and data (Q3 – Q0) and terminal count (TC) outputs go to logic level zero, independent of clock transitions. The outputs (Q3 – Q0) increment when clock enable (CE) is High during the Lowto- High clock (C) transition. The counter ignores clock transitions when CE is Low. The TC output is High when Q3 and Q0 are High and Q2 and Q1 are Low.

Larger counters are created by connecting the count enable out (CEO) output of the first stage to the CE input of the next stage and connecting the CLR and clock inputs in parallel. CEO is active (High) when TC and CE are High. The maximum length of the counter is determined by the accumulated CE-to-TC propagation delays versus the clock period. The clock period must be greater than n(tCE-TC), where “n” is the number of stages and “tCE-TC” is the CE-to-TC propagation delay of each stage.

When cascading counters, use the CEO output if the counter uses the CE input; use the TC output if it does not.

Parameters