State Machine

The digital state machine provides for straightforward descriptions of clocked combinational logic blocks with a variable number of inputs and outputs and with an unlimited number of possible states. The model can be configured to behave as virtually any type of counter or clocked combinational logic block and can be used to replace very large digital circuit schematics with an identically functional but faster representation.

The DSTATE model is configured through the use of a state definition source text. The file defines all states to be understood by the model, plus input bit combinations which trigger changes in state. An example source text is shown below:

* This file defines a simple 2-bit counter with one input. 
* The value of this input determines whether the counter 
* counts up (in = 1) or down (in = 0).
*STATE D0 D1 I0 -> NEXT

0 0 0 0 -> 3
1 -> 1
1 0 1 0 -> 0
1 -> 2
2 1 0 0 -> 1
1 -> 3
3 1 1 0 -> 2 3 1 1 1 -> 0

Several attributes of the above source text structure should be noted. First, ALL LINES IN THE FILE MUST BE ONE OF FOUR TYPES. These are:

  1. A comment, beginning with a "*" in the first column.
  2. A header line, which is a complete description of the current state, the outputs corresponding to that state, an input value, and the state that the model will assume should that input be encountered. The first line of a state definition must ALWAYS be a header line.
  3. A continuation line, which is a partial description of a state, consisting of an input value and the state that the model will assume should that input be encountered. Note that continuation lines may only be used after the initial header line definition for a state.
  4. A line containing nothing but whitespace (space, newline).

A line which is not one of the above will cause a file-loading error.

Note that in the example shown, whitespace (any combination of blanks, tabs, commas) is used to separate values, and that the character "->" is used to underline the state transition implied by the input preceding it. This particular character is not critical in of itself, and can be replaced with any other character or non-broken combination of characters that you prefer (e.g. "==>", ">>, ":", "resolves _to", etc.)

The order of the output and input bits in the file is important; the first column is always interpreted to refer to the "zeroth" bit of input and output. Thus, in the file above, the output from state 1 sets out[0] to "0", and out[1] to "1".

The state numbers need not be in any particular order, but a state definition (which consists of the sum total of all lines which define the state, its outputs, and all methods by which a state can be exited) must be made on contiguous line numbers; a state definition cannot be broken into sub-blocks and distributed randomly throughout the file. On the other hand, the state definition can be broken up by as many comment lines as you desire.

Input Values

Value State
0, L Low
1, H High
U, X Unknown

Output Values

Value State
0, L Low
1, H High
U, X Unknown
Z Hi-Z

Parameters

Parameter Description Units Default
SOURCE Source text.    
CLK_DELAY Delay from CLK. s DGTDELAY
RESET_DELAY Delay from reset. s DGTDELAY
RESET_STATE Default state on RESET and at DC.   0
IN_MODE Inputs mode.   IN
OUT_MODE Outputs mode.   OUT
IOMODEL The name of an I/O model, which describes the device‚Äôs loading and driving characteristics.   DGTDEFIOMODEL
POWER_NODE Digital power node name. Is the node used by the interface subcircuits which connect analog nodes to digital nodes.   $G_DPWR
GROUND_NODE Digital ground node name. Is the node used by the interface subcircuits which connect analog nodes to digital nodes.   $G_DGND

Error Messages

D_STATE: Source text was not read successfully.

This error occurs when the source text has not been read successfully. This is due to one of the following:

  • The counted number of tokens in one of the file's input lines does not equal that required to define either a state header or a continuation line (Note that all comment lines are ignored, so these will never cause the error to occur).
  • An output state value was defined using a symbol which was invalid.
  • An input value was defined using a symbol which was invalid.
D_STATE: An error exists in the ordering of states values.

This error is caused by the different state definitions in the input file being non-contiguous. In general, it will refer to the different states not being defined uniquely, or being "broken up" in some fashion within the source text.