D Flip-Flop with Asynchronous Clear
FDC is a single D-type flip-flop with data (D) and asynchronous clear (CLR) inputs and data output (Q). The asynchronous CLR, when High, overrides all other inputs and sets the Q output Low. The data on the D input is loaded into the flip-flop when CLR is Low on the Low-to-High clock transition.
Parameters
| Parameter | Description | Units | Default |
|---|---|---|---|
| IC | Output initial state. | LOW | |
| CLKTPLH | Delay from clock to out high. | s | DGTDELAY |
| CLKTPHL | Delay from clock to out low. | s | DGTDELAY |
| CLRTPLH | Delay from clear to out high. | s | DGTDELAY |
| CLRTPHL | Delay from clear to out low. | s | DGTDELAY |
| IN_MODE | Inputs mode. | IN | |
| OUT_MODE | Outputs mode. | OUT | |
| IOMODEL | The name of an I/O model, which describes the device’s loading and driving characteristics. | DGTDEFIOMODEL | |
| POWER_NODE | Digital power node name. Is the node used by the interface subcircuits which connect analog nodes to digital nodes. | $G_DPWR | |
| GROUND_NODE | Digital ground node name. Is the node used by the interface subcircuits which connect analog nodes to digital nodes. | $G_DGND |