D Flip-Flop with Clock Enable and Asynchronous Preset

FDPE is a single D-type flip-flop with data (D), clock enable (CE), and asynchronous preset (PRE) inputs and data output (Q). The asynchronous PRE, when High, overrides all other inputs and sets the Q output High. Data on the D input is loaded into the flip-flop when PRE is Low and CE is High on the Low-to-High clock (C) transition. When CE is Low, the clock transitions are ignored. The default initial state of the flip-flop is zero.

Parameters

Parameter Description Units Default
IC Output initial state.   LOW
CLKTPLH Delay from clock to out high. s DGTDELAY
CLKTPHL Delay from clock to out low. s DGTDELAY
PRETPLH Delay from preset to out high. s DGTDELAY
PRETPHL Delay from preset to out low. s DGTDELAY
IN_MODE Inputs mode.   IN
OUT_MODE Outputs mode.   OUT
IOMODEL The name of an I/O model, which describes the device‚Äôs loading and driving characteristics.   DGTDEFIOMODEL
POWER_NODE Digital power node name. Is the node used by the interface subcircuits which connect analog nodes to digital nodes.   $G_DPWR
GROUND_NODE Digital ground node name. Is the node used by the interface subcircuits which connect analog nodes to digital nodes.   $G_DGND