J-K Flip-Flop with Clock Enable and Asynchronous Preset
FJKPE is a single J-K-type flip-flop with J, K, clock enable (CE), and asynchronous preset (PRE) inputs and data output (Q). The asynchronous preset (PRE), when high, overrides all other inputs and sets the Q output High. When PRE is Low and CE is High, the Q output responds to the state of the J and K inputs, according to the following truth table, during the Low-to-High clock (C) transition. When CE is Low, clock transitions are ignored. The default initial state of the flip-flop is zero.
| Inputs | Output | ||||
|---|---|---|---|---|---|
| PRE | CE | J | K | C | Q |
| 1 | X | X | X | X | 1 |
| 0 | 0 | X | X | X | No Chg |
| 0 | 1 | 0 | 0 | X | No Chg |
| 0 | 1 | 0 | 1 | ↑ | 0 |
| 0 | 1 | 1 | 0 | ↑ | 1 |
| 0 | 1 | 1 | 1 | ↑ | Toggle |
Parameters
| Parameter | Description | Units | Default | |
|---|---|---|---|---|
| IC | Output initial state. | LOW | ||
| CLKTPLH | Delay from clock to out high. | s | DGTDELAY | |
| CLKTPHL | Delay from clock to out low. | s | DGTDELAY | |
| PRETPLH | Delay from preset to out high. | s | DGTDELAY | |
| PRETPHL | Delay from preset to out low. | s | DGTDELAY | |
| IN_MODE | Inputs mode. | IN | ||
| OUT_MODE | Outputs mode. | OUT | ||
| IOMODEL | The name of an I/O model, which describes the device’s loading and driving characteristics. | DGTDEFIOMODEL | ||
| POWER_NODE | Digital power node name. Is the node used by the interface subcircuits which connect analog nodes to digital nodes. | $G_DPWR | ||
| GROUND_NODE | Digital ground node name. Is the node used by the interface subcircuits which connect analog nodes to digital nodes. | $G_DGND |