Toggle Flip-Flop with Toggle Enable and Asynchronous Clear and Preset

When the asynchronous clear (CLR) input is High, all other inputs are ignored and the output (Q) is reset Low. When the asynchronous preset (PRE) input is High, all other inputs are ignored and Q is set High. When the toggle enable input (T) is High and CLR and PRE are Low, output Q toggles, or changes state, during the Low-to-High clock (C) transition. When both PRE and CLR are active, the flip-flop output is unpredictable.

Parameters

Parameter Description Units Default
IC Output initial state.   LOW
CLKTPLH Delay from clock to out high. s DGTDELAY
CLKTPHL Delay from clock to out low. s DGTDELAY
PRETPLH Delay from preset to out high. s DGTDELAY
PRETPHL Delay from preset to out low. s DGTDELAY
CLRTPLH Delay from clear to out high. s DGTDELAY
CLRTPHL Delay from clear to out low. s DGTDELAY
IN_MODE Inputs mode.   IN
OUT_MODE Outputs mode.   OUT
IOMODEL The name of an I/O model, which describes the device’s loading and driving characteristics.   DGTDEFIOMODEL
POWER_NODE Digital power node name. Is the node used by the interface subcircuits which connect analog nodes to digital nodes.   $G_DPWR
GROUND_NODE Digital ground node name. Is the node used by the interface subcircuits which connect analog nodes to digital nodes.   $G_DGND