Toggle/Loadable Flip-Flop with Toggle and Clock Enable and Asynchronous Preset

When the asynchronous preset input (PRE) is High, all other inputs are ignored and output Q is set High during the Low-to-High clock (C) transition. When the load enable input (L) is High and PRE is Low, the clock enable (CE) is overridden and the data on input (D) is loaded into the flip-flop during the Low-to-High clock transition. When L and PRE are Low and toggle enable input (T) and CE are High, output Q toggles, or changes state, during the Low-to-High clock transition. When CE is Low, clock transitions are ignored.

Parameters

Parameter Description Units Default
IC Output initial state.   LOW
CLKTPLH Delay from clock to out high. s DGTDELAY
CLKTPHL Delay from clock to out low. s DGTDELAY
PRETPLH Delay from preset to out high. s DGTDELAY
PRETPHL Delay from preset to out low. s DGTDELAY
IN_MODE Inputs mode.   IN
OUT_MODE Outputs mode.   OUT
IOMODEL The name of an I/O model, which describes the device‚Äôs loading and driving characteristics.   DGTDEFIOMODEL
POWER_NODE Digital power node name. Is the node used by the interface subcircuits which connect analog nodes to digital nodes.   $G_DPWR
GROUND_NODE Digital ground node name. Is the node used by the interface subcircuits which connect analog nodes to digital nodes.   $G_DGND