16-Bit Loadable Serial/Parallel-In Parallel-Out Shift Register with Clock Enable and Synchronous Reset

SR16RLE is a 16-bit shift register with shift-left serial input (SLI), parallel inputs (D15 – D0), parallel outputs (Q15 – Q0), and control inputs – clock enable (CE), load enable (L), and synchronous reset (R). The register ignores clock transitions when L and CE are Low. The synchronous R, when High, overrides all other inputs and resets the data outputs (Q15 – Q0) Low. When L is High and R is Low, data on the data D15 – D0 inputs is loaded into the corresponding Q15 – Q0 bits of the register. When CE is High and L and R are Low, data on the SLI is loaded into the first bit of the shift register during the Low-to- High clock (C) transition and appears on the Q0 output. During subsequent clock transitions, when CE is High and L and R are Low, the data is shifted to the next highest bit position as new data is loaded into Q0 (SLI->Q0, Q0->Q1, Q1->Q2, and so forth). Registers can be cascaded by connecting the Q15 output of one stage to the Shift Left Input (SLI) of the next stage and connecting clock, CE, L, and R inputs in parallel.

The default initial state of all flip-flops is zero.

Parameters