4-Bit Loadable Serial/Parallel-In Parallel-Out Shift Register with Clock Enable and Asynchronous Clear

SR4CLE is a 4-bit shift register with a shift-left serial input (SLI), parallel inputs (D3 – D0), parallel outputs (Q3 – Q0), and three control inputs – clock enable (CE), load enable (L), and asynchronous clear (CLR).The register ignores clock transitions when L and CE are Low. The asynchronous CLR, when High, overrides all other inputs and resets the data outputs (Q3 – Q0) Low. When L is High and CLR is Low, data on the D3 – D0 inputs is loaded into the corresponding Q3 – Q0 bits of the register. When CE is High and L and CLR are Low, data on the SLI input is loaded into the first bit of the shift register during the Low-to-High clock (C) transition and appears on the Q0 output. During subsequent clock transitions, when CE is High and L and CLR are Low, the data is shifted to the next highest bit position as new data is loaded into Q0 (SLI->Q0, Q0->Q1, Q1->Q2, and so forth).

Registers can be cascaded by connecting the Q3 output of one stage to the SLI input of the next stage and connecting clock, CE, L, and CLR inputs in parallel.

The default initial state of all flip-flops is zero.

Parameters