D Latch

The digital d-type latch is a one-bit, level-sensitive storage element which will output the value on the data line whenever the enable input line is high (ONE). The value on the data line is stored (i.e., held on the out line) whenever the enable line is low (ZERO).

In addition, asynchronous set and reset signals exist, and each of the four methods of changing the stored output of the d_dlatch (i.e., data changing with enable=ONE, enable changing to ONE from ZERO with a new value on data, raising set and raising reset) have separate delays associated with them.

Port Table

Description Direction Default Type Allowed Types Vector Vector Bounds Null Allowed
input data IN d d NO   NO
enable IN d d NO   NO
set IN d d NO   YES
reset IN d d NO   YES
data output OUT d d NO   YES
inverted data output OUT d d NO   YES

Parameter Table

Name Description Data Type Default Value Limits Vector Vector Bounds Null Allowed
DELAY generic delay Real 1.0e-9 1e-12 / - NO   YES
DTPLH delay from data to out high Real 0 1e-12 / - NO   YES
DTPHL delay from data to out low Real 0 1e-12 / - NO   YES
LETPLH delay from enable to out high Real 0 1e-12 / - NO   YES
LETPHL delay from enable to out low Real 0 1e-12 / - NO   YES
PRETPLH delay from set to out high Real 0 1e-12 / - NO   YES
PRETPHL delay from set to out low Real 0 1e-12 / - NO   YES
CLRTPLH delay from reset to out high Real 0 1e-12 / - NO   YES
CLRTPHL delay from reset to out low Real 0 1e-12 / - NO   YES
IC output initial state (0=low, 1=high, 2=unknown) Int 0 0 / 2 NO   YES
DATA_LOAD data load value (F) Real 1.0e-12   NO   YES
ENABLE_LOAD enable load value (F) Real 1.0e-12   NO   YES
SET_LOAD set load value (F) Real 1.0e-12   NO   YES
RESET_LOAD reset load value (F) Real 1.0e-12   NO   YES

Example

a4 12 4 5 6 3 14 latch1
  
.model latch1 d_dlatch(delay = 13.0e-9)

See also

XSPICE Devices
XSPICE Code Models