D_OSC |

Controlled Digital Oscillator

The digital oscillator is a hybrid model which accepts as input a voltage or
current. This input is compared to the voltage-to-frequency transfer
characteristic specified by the cntl_array/freq_array coordinate pairs, and
a frequency is obtained which represents a linear interpolation or
extrapolation based on those pairs. A digital time-varying signal is then
produced with this fundamental frequency.

The output waveform, which
is the equivalent of a digital clock signal, has rise and fall delays which
can be specified independently. In addition, the duty cycle and the phase of
the waveform are also variable and can be set by you.

Description | Direction | Default Type | Allowed Types | Vector | Vector Bounds | Null Allowed |

control input | IN | v | v,vd,i,id | NO | NO | |

Output | OUT | d | d | NO | NO |

Name | Description | Data Type | Default Value | Limits | Vector | Vector Bounds | Null Allowed |

cntl_array | control array | Real | 0.0 | YES | 2 / - | NO | |

freq_array | frequency array | Real | 1.0e6 | 0 / - | YES | 2 / - | NO |

duty_cycle | output duty cycle | Real | 0.5 | 1.0e-6 / 0.999999 | NO | YES | |

init_phase | initial phase of output | Real | 0.0 | -180.0 / +360.0 | NO | YES | |

rise_delay | rise delay | Real | 1.0e-9 | 0 / - | NO | YES | |

fall_delay | fall delay | Real | 1.0e-9 | 0 / - | NO | YES |

`D_0SC: Error allocating VCO block storage`

Generic block storage allocation error.

`D_0SC: Size of control array different than frequency array`

Error occurs when there is a different number of control array members than frequency array members.

```
D_0SC: The extrapolated value for frequency
has been found to be negative...
Lover frequency level has been clamped to 0.0 Hz.
```

Occurs whenever a control voltage is input to a model which would ordinarily (given the specified control/freq coordinate points) cause that model to attempt to generate an output oscillating at zero frequency. In this case, the output will be clamped to some DC value until the control voltage returns to a more reasonable value.

```
a5 1 8 var_clock
.model var_clock d_osc(cntl_array = [-2 -1 1 2]
+ freq.array = [le3 le3 10e3 10e3]
+ duty.cycle = 0.4 init_phase = 180.0
+ rise_delay = 10e-9 fall_delay = 8e-9)
```