SOP

The digital 'sop' gate is an n-input, single-output gate which provide common logic functions by OR gating the outputs of two AND functions. The delays associated with an output rise and those associated with an output fall may be specified independently. The model also posts an input load value (in farads) based on the parameter input_load. The output of this model does NOT, however, respond to the total loading it sees on its output; it will always drive the output strongly with the specified delays.

Port Table

Description Direction Default Type Allowed Types Vector Vector Bounds Null Allowed
Inputs AND A IN d d YES 1 / - NO
Inputs AND B IN d d YES 1 / - NO
Output (A+B) OUT d d NO   NO

Parameter Table

Name Description Data Type Default Value Limits Vector Vector Bounds Null Allowed
rise_delay rise delay Real 1.0e-9 1.0e-12 / - NO   YES
fall_delay fall delay Real 1.0e-9 1.0e-12 / - NO   YES
input_load input load value (F) Real 1.0e-12   NO   YES

Example

a6 [1 2] [3 4] 5 sop1
  
.model sop1 d_sop(rise_delay = 0.5e-9 fall_delay = 0.3e-9 input.load = 0.5e-12)

See also

XSPICE Devices
XSPICE Code Models