Set-Reset Flip Flop

The digital sr-type flip flop is a one-bit, edge-triggered storage element which will store data whenever the clk input line transitions from low to high (ZERO to ONE). The value stored (i.e., the "out" value) will depend on the s and r input pin values, and will be:

S R OUT
ZERO ZERO current value
ZERO ONE ZERO
ONE ZERO ONE
ONE ONE UNKNOWN

In addition, set and reset signals exist, and each of the three methods of changing the stored output of the d_srff have separate load values and delays associated with them.

Port Table

Description Direction Default Type Allowed Types Vector Vector Bounds Null Allowed
s input IN d d NO   NO
r input IN d d NO   NO
clock IN d d NO   NO
clock enable IN d d NO   YES
set IN d d NO   YES
reset IN d d NO   YES
data output OUT d d NO   YES
inverted data output OUT d d NO   YES

Parameter Table

Name Description Data Type Default Value Limits Vector Vector Bounds Null Allowed
DELAY generic delay Real 1.0e-9 1e-12 / - NO   YES
CLKTPLH delay from clock to out high Real 0 1e-12 / - NO   YES
CLKTPHL delay from clock to out low Real 0 1e-12 / - NO   YES
PRETPLH delay from set to out high Real 0 1e-12 / - NO   YES
PRETPHL delay from set to out low Real 0 1e-12 / - NO   YES
CLRTPLH delay from reset to out high Real 0 1e-12 / - NO   YES
CLRTPHL delay from reset to out low Real 0 1e-12 / - NO   YES
IC output initial state (0=low, 1=high, 2=unknown) Int 0 0 / 2 NO   YES
SR_LOAD s,r load values (F) Real 1.0e-12   NO   YES
CLK_LOAD clk load value (F) Real 1.0e-12   NO   YES
SET_LOAD set load value (F) Real 1.0e-12   NO   YES
RESET_LOAD reset load value (F) Real 1.0e-12   NO   YES
CLKENABLE_LOAD clock enable load value (F) Real 1.0e-12   NO   YES
MODE 0=asynchronous Set and Reset.
1=synchronous mode. Reset has precedence over Set.
3=synchronous mode. Set has precedence over Reset. 		Int 0   NO   YES

Example

a8 2 12 4 5 6 3 14 flop7
  
.model flop7 d_srff(delay=13.0e-9)

See also

XSPICE Devices
XSPICE Code Models