The digital sr-type latch is a one-bit, level-sensitive storage element
which will output the value dictated by the state of the s and r pins
whenever the enable input line is high (ONE). This value is stored (i.e.,
held on the out line) whenever the enable line is low (ZERO). The particular
value chosen is as shown below:
S
R
OUT
ZERO
ZERO
current value
ZERO
ONE
ZERO
ONE
ZERO
ONE
ONE
ONE
UNKNOWN
Asynchronous set and reset signals exist, and each of the four methods of
changing the stored output of the d-srlatch (i.e., s/r combination changing
with enable=ONE, enable changing to ONE from ZERO with an output-changing
combination of s and r, raising set and raising reset) have separate delays
associated with them.