| D_TABLE |
Truth Table
The d_table block sets output logic states based on truth table. The model
can be configured to behave as virtually any type of counter or
combinational logic block and can be used to replace very large digital
circuit schematics with an identically functional but faster representation.
The d_table model is configured through the use of a table definition
file. The file defines the truth table function used to set the level and
strength of the specified outputs.
example 1:
*----- begin Flip-Flop file ------
CLR PRE CE D C | Q
| 1
*---------------------------------
H L X X X | L (param1)
L H X X X | H (param2)
L L L X X | Q
L L H L R | L
L L H H R | H
*---------- end file -------------
example 2:
*--- begin comparator file ----
A[2] B[2] | EQ
*------------------------------
X X | A==B
*-------- end file ------------
example 3:
*------------ begin counter file -----------------
CLR LD CE C UP D[2] | Q[2] TC CEO
*-------------------------------------------------
1 X X X X X | L L L
0 1 X R X X | D TC CEO
0 0 1 R 1 X | Inc TC CEO 10n
0 0 1 R 0 X | Dec TC CEO 10n
0 X X X X X | Q TC CEO
*-------------------------------------------------
#TC = ((Q==3) && UP) || ((Q==0) && !UP)
#CEO = (((Q==3) && UP) || ((Q==0) && !UP)) && (CE)
*--------------- end file ------------------------
A comment, beginning with a * in the first column. In a row everything after the ; is considered a comment and removed.
The first line is the header and list the inputs and outputs. First, the inputs are specified and then separated by | are specified the outputs. The order of the inputs and outputs is the same as the definition of the component. The name of the inputs and outputs are only used as a reference in the table and have no relation to the actual names of the pins.
The vectors of input and output use square brackets to enclose width. eg. DATA[8]. When an output vector is used as input, only the name must be specified. No spaces are allowed in vector definition.
The outputs are updated from left to right, therefore the outputs that depend on other outputs should be specified after these. To use the output port state before it was upgraded you have to prefix the port name with the underscore character.
If in the table header the input ports are listed in a different order from the definition of the component use the @ prefix to define the list of inputs and outputs.
The input column with name ? represents a column of conditional expressions. The corresponding line will be considered only if the expression is verified.
If a line begins with the text @I is a definition of the inputs. The order of the inputs is the same as the definition of the component. The name of the inputs and outputs are only used as a reference in the table and have no relation to the actual names of the pins. Use this form to define the inputs that are not present in the header of the table but are used in expressions or if in the table header the input ports are listed in a different order from the definition of the component. The form is the following:
@I [startindex] <inp> [inp...] [@I <startindex> <inp> [inp...]]
Examples:
@I 0 D[4] CLK EN ;D is a vector at index
0..3, CLK is at index 4, EN is at index 5
@I
D[4] CLK EN ;D is a vector at index 0..3, CLK is at index 4, EN
is at index 5
@I D[4] CLK EN @I 0 D3 D2 D1 D0
;D is a vector at index 0..3, CLK is at index 4, EN is at index 5, D3 is bit
3 of vector D at index 0, D2 is bit 2 of vector D at index 1, D1 is bit 1 of
vector D at index 2, D0 is bit 0 of vector D at index 3
If a line begins with the text @O is a definition of the outputs. The order of the outputs is the same as the definition of the component. The name of the inputs and outputs are only used as a reference in the table and have no relation to the actual names of the pins. Use this form to define the outputs that are not present in the header of the table but are used in expressions or if in the table header the output ports are listed in a different order from the definition of the component. The form is the following:
@O [startindex] <out> [out...] [@O <startindex> <out> [out...]]
The expressions placed within the table should not contain spaces or must be enclosed by parentheses (see example 2).
If a line begins with a # character is considered a definition of an expression (see example 3). The form is the following:
#<name> = <definition of the expression>
In the output expressions the state of an output port corresponds to the state of the port after it has been changed. To use the port status before it was upgraded you have to prefix the port name with the underscore character.
The interface parameters (delay, param1 .. param10) can be used in expressions (see example 1).
At the end of each row can optionally be specified the output delay if is different from the default specified by the delay parameter (see examples 1 and 3).
Each row is tested sequentially from top to bottom until the input condition are met. The outputs are set for the first row to meet the input conditions.
If a row begins with the character | is the initialization row of the outputs. If you do not specify an initialization row all outputs are initialized to the zero state (see example 1).
| Value | State |
| L | Low. |
| 0 | Low. |
| H | High. |
| 1 | High. |
| R | Rise. Low to High transition. |
| F | Fall. High to Low transition. |
| X | Don't care. |
| expression | Use input expression. |
| number | Decimal number. Only for vectors. |
| $xxxx | Hexadecimal number. Only for vectors. $1A |
| %xxxx | Binary number. Only for vectors. %0101 |
| Value | State |
| L | Low. For vectors indicates all bits 0. |
| 0 | Low. For vectors is number 0. |
| H | High. For vectors indicates all bits 1. |
| 1 | High. For vectors is number 1. |
| Z | Unknown. |
| X | Invalid state. A random value (H or L). |
| Inc | Increment. Only for vectors. |
| Dec | Decrement. Only for vectors. |
| expression | Use output expression. |
| input | State of referenced input. |
| output | State of referenced output. |
| number | Decimal number. Only for vectors. |
| $xxxx | Hexadecimal number. Only for vectors. $1A |
| %xxxx | Binary number. Only for vectors. %0101 |
| <0(n)Port | Shift left with load 0 of vector port. (n) and Port are optional. default n=1. |
| <1(n)Port | Shift left with load 1 of vector port. (n) and Port are optional. default n=1. |
| <+(n)Port | Shift Rotate left of vector port. (n) and Port are optional. default n=1. |
| <-(n)Port | Shift Rotate inverted left of vector port. (n) and Port are optional. default n=1. |
| <(n)Port | Shift left of vector port. (n) and Port are optional. default n=1. |
| 0>(n)Port | Shift right with load 0 of vector port. (n) and Port are optional. default n=1. |
| 1>(n)Port | Shift right with load 1 of vector port. (n) and Port are optional. default n=1. |
| +>(n)Port | Shift Rotate right of vector port. (n) and Port are optional. default n=1. |
| ->(n)Port | Shift Rotate inverted right of vector port. (n) and Port are optional. default n=1. |
| >(n)Port | Shift right of vector port. (n) and Port are optional. default n=1. |
It also allows Input and Output pin names with optional prefixes to specify
the output states. Prefixes are:
| Prefix | Description |
| ~ | State is the inverse of the state. |
| _ | State is the previous state. |
Output state letters can be followed by a suffix to indicate strength (eg. Hr).
| Suffix | Strength |
| s | STRONG. |
| r | RESISTIVE. |
| z | HI_IMPEDANCE. |
| u | UNDETERMINED. |
If a strength character is not specified after an output state then STRONG
will be used for L and H states and HI_IMPEDANCE will be used for Z states.
| Description | Direction | Default Type | Allowed Types | Vector | Vector Bounds | Null Allowed |
| input | IN | d | d | YES | 1 / - | NO |
| output | OUT | d | d | YES | 1 / - | NO |
| Name | Description | Data Type | Default Value | Limits | Vector | Vector Bounds | Null Allowed |
| delay | default delay | Real | 1.0e-9 | NO | YES | ||
| table_file | table specification file name | String | table.txt | NO | NO | ||
| input_load | input loading capacitance (F) | Real | 1.0e-12 | NO | YES | ||
| param1 | parameter 1 | Real | 0.0 | NO | YES | ||
| param2 | parameter 2 | Real | 0.0 | NO | YES | ||
| param3 | parameter 3 | Real | 0.0 | NO | YES | ||
| param4 | parameter 4 | Real | 0.0 | NO | YES | ||
| param5 | parameter 5 | Real | 0.0 | NO | YES | ||
| param6 | parameter 6 | Real | 0.0 | NO | YES | ||
| param7 | parameter 7 | Real | 0.0 | NO | YES | ||
| param8 | parameter 8 | Real | 0.0 | NO | YES | ||
| param9 | parameter 9 | Real | 0.0 | NO | YES | ||
| param10 | parameter 10 | Real | 0.0 | NO | YES |
If the filename contains spaces must be delimited by quotation marks. If you do not specify a full path, the file is searched in the following order:
If the file name is not delimited by quotation marks then the table is searched first in the current netlist as a data block specified by the command .DATA.
D_TABLE: Table file 'table.txt' not found.
This message is displayed each time the specified file does not exist.
D_TABLE: Invalid Table header.
This error occurs when there is an error in the header of the table.
D_TABLE: Invalid Table description.
This error occurs when there is an error in the rows of the table.
D_TABLE: Invalid expression.
This error occurs when there is an error in the expression.
a4 [1 2 3] [4 5 6 7] tablemodel
.model tablemodel d_table(delay = 13.0e-9 table_file = "example3.txt")
a5 [1 2 3 4 5] [6] ffmodel
.model ffmodel d_table(delay=10ns table_file=fftable param1=8ns param2=5ns)
.DATA fftable
*----- begin Flip-Flop table -----
CLR PRE CE D C | Q
*---------------------------------
H L X X X | L (param1)
L H X X X | H (param2)
L L L X X | Q
L L H L R | L
L L H H R | H
*---------- end table ------------
.ENDD