16-Bit Negative-Edge Binary Ripple Counter with Clock Enable and Asynchronous Clear

CR16CE is a 16-bit, cascadable, clearable, binary, ripple counter. The asynchronous clear (CLR), when High, overrides all other inputs and causes the outputs (Q15 – Q0) to go to logic level zero. The counter increments when the clock enable input (CE) is High during the High-to-Low clock (C) transition. The counter ignores clock transitions when CE is Low.

Larger counters can be created by connecting the Q15 output of the first stage to the clock input of the next stage. CLR and CE inputs are connected in parallel. The clock period is not affected by the overall length of a ripple counter. The overall clock-to-output propagation is n(TC - Q), where n is the number of stages and TC - Q is the C-to-Q15 propagation delay of each stage.

Parameters

Parameter Description Units Default
DELAY Propagation delay. s DGTDELAY
IN_MODE Inputs mode.   IN
OUT_MODE Outputs mode.   OUT
IOMODEL The name of an I/O model, which describes the device’s loading and driving characteristics.   DGTDEFIOMODEL
POWER_NODE Digital power node name. Is the node used by the interface subcircuits which connect analog nodes to digital nodes.   $G_DPWR
GROUND_NODE Digital ground node name. Is the node used by the interface subcircuits which connect analog nodes to digital nodes.   $G_DGND