Frequency Divider
The digital frequency divider is a programmable step-down divider which accepts an arbitrary divisor (div_factor), a duty-cycle term (high_cycles), and an initial count value (i_count). The generated output is synchronized to the rising edges of the input signal. Rise delay and fall delay on the outputs may also be specified independently.
Parameters
| Parameter | Description | Units | Default |
|---|---|---|---|
| DIV_FACTOR | Divide factor. | 2 | |
| HIGH_CYCLES | Number of high clock cycles. | 1 | |
| I_COUNT | Output initial count value. | 0 | |
| FALL_DELAY | Fall delay. | s | DGTDELAY |
| RISE_DELAY | Rise delay. | s | DGTDELAY |
| IN_MODE | Inputs mode. | IN | |
| OUT_MODE | Outputs mode. | OUT | |
| IOMODEL | The name of an I/O model, which describes the device’s loading and driving characteristics. | DGTDEFIOMODEL | |
| POWER_NODE | Digital power node name. Is the node used by the interface subcircuits which connect analog nodes to digital nodes. | $G_DPWR | |
| GROUND_NODE | Digital ground node name. Is the node used by the interface subcircuits which connect analog nodes to digital nodes. | $G_DGND |