D Flip-Flop with Synchronous Reset and Synchronous Set
FDRS is a single D-type flip-flop with data (D), synchronous set (S), and synchronous reset (R) inputs and data output (Q). The synchronous reset (R) input, when High, overrides all other inputs and resets the Q output Low during the Low-to-High clock (C) transition. (Reset has precedence over Set.) When S is High and R is Low, the flip-flop is set, output High, during the Low-to-High clock transition. When R and S are Low, data on the (D) input is loaded into the flip-flop during the Low-to-High clock transition.
Parameters
Parameter | Description | Units | Default |
---|---|---|---|
IC | Output initial state. | LOW | |
CLKTPLH | Delay from clock to out high. | s | DGTDELAY |
CLKTPHL | Delay from clock to out low. | s | DGTDELAY |
PRETPLH | Delay from set to out high. | s | DGTDELAY |
PRETPHL | Delay from set to out low. | s | DGTDELAY |
CLRTPLH | Delay from reset to out high. | s | DGTDELAY |
CLRTPHL | Delay from reset to out low. | s | DGTDELAY |
IN_MODE | Inputs mode. | IN | |
OUT_MODE | Outputs mode. | OUT | |
IOMODEL | The name of an I/O model, which describes the device’s loading and driving characteristics. | DGTDEFIOMODEL | |
POWER_NODE | Digital power node name. Is the node used by the interface subcircuits which connect analog nodes to digital nodes. | $G_DPWR | |
GROUND_NODE | Digital ground node name. Is the node used by the interface subcircuits which connect analog nodes to digital nodes. | $G_DGND |