D Flip-Flop with Clock Enable and Synchronous Set
FDSE is a single D-type flip-flop with data (D), clock enable (CE), and synchronous set (S) inputs and data output (Q). The synchronous set (S) input, when High, overrides the clock enable (CE) input and sets the Q output High during the Low-to-High clock (C) transition. The data on the D input is loaded into the flip-flop when S is Low and CE is High during the Low-to-High clock (C) transition.
Parameters
| Parameter | Description | Units | Default |
|---|---|---|---|
| IC | Output initial state. | LOW | |
| CLKTPLH | Delay from clock to out high. | s | DGTDELAY |
| CLKTPHL | Delay from clock to out low. | s | DGTDELAY |
| PRETPLH | Delay from set to out high. | s | DGTDELAY |
| PRETPHL | Delay from set to out low. | s | DGTDELAY |
| IN_MODE | Inputs mode. | IN | |
| OUT_MODE | Outputs mode. | OUT | |
| IOMODEL | The name of an I/O model, which describes the device’s loading and driving characteristics. | DGTDEFIOMODEL | |
| POWER_NODE | Digital power node name. Is the node used by the interface subcircuits which connect analog nodes to digital nodes. | $G_DPWR | |
| GROUND_NODE | Digital ground node name. Is the node used by the interface subcircuits which connect analog nodes to digital nodes. | $G_DGND |