J-K Flip-Flop with Clock Enable and Asynchronous Clear
FJKCE is a single J-K-type flip-flop with J, K, clock enable (CE), and asynchronous clear (CLR) inputs and data output (Q). The asynchronous clear (CLR), when High, overrides all other inputs and resets the Q output Low. When CLR is Low and CE is High, Q responds to the state of the J and K inputs, as shown in the following truth table, during the Low-to-High clock transition. When CE is Low, the clock transitions are ignored. The default initial state of the flip-flop is zero.
| Inputs | Output | ||||
|---|---|---|---|---|---|
| CLR | CE | J | K | C | Q |
| 1 | X | X | X | X | 0 |
| 0 | 0 | X | X | X | No Chg |
| 0 | 1 | 0 | 0 | X | No Chg |
| 0 | 1 | 0 | 1 | ↑ | 0 |
| 0 | 1 | 1 | 0 | ↑ | 1 |
| 0 | 1 | 1 | 1 | ↑ | Toggle |
Parameters
| Parameter | Description | Units | Default |
|---|---|---|---|
| IC | Output initial state. | LOW | |
| CLKTPLH | Delay from clock to out high. | s | DGTDELAY |
| CLKTPHL | Delay from clock to out low. | s | DGTDELAY |
| CLRTPLH | Delay from clear to out high. | s | DGTDELAY |
| CLRTPHL | Delay from clear to out low. | s | DGTDELAY |
| IN_MODE | Inputs mode. | IN | |
| OUT_MODE | Outputs mode. | OUT | |
| IOMODEL | The name of an I/O model, which describes the device’s loading and driving characteristics. | DGTDEFIOMODEL | |
| POWER_NODE | Digital power node name. Is the node used by the interface subcircuits which connect analog nodes to digital nodes. | $G_DPWR | |
| GROUND_NODE | Digital ground node name. Is the node used by the interface subcircuits which connect analog nodes to digital nodes. | $G_DGND |