J-K Flip-Flop with Asynchronous Clear and Preset and Clock Enable
FJKCPE is a single J-K-type flip-flop with J, K, asynchronous clear (CLR), asynchronous preset (PRE), and clock enable (CE) inputs and data output (Q). The asynchronous clear input (CLR), when High, overrides all other inputs and resets the Q output Low. The asynchronous preset (PRE) input, when High, overrides all other inputs and sets the Q output High. When both CLR and PRE are active, the flipflop output is unpredictable. When CLR and PRE are Low and CE is High, Q responds to the state of the J and K inputs, as shown in the following truth table, during the Low-to-High clock transition. Clock transitions are ignored when CE is Low. The default initial state of the flip-flop is zero.
| Inputs | Output | |||||
|---|---|---|---|---|---|---|
| CLR | PRE | CE | J | K | C | Q |
| 1 | 0 | X | X | X | X | 0 |
| 0 | 1 | X | X | X | X | 1 |
| 0 | 0 | 0 | X | X | X | No Chg |
| 0 | 0 | 1 | 0 | 0 | X | No Chg |
| 0 | 0 | 1 | 0 | 1 | ↑ | 0 |
| 0 | 0 | 1 | 1 | 0 | ↑ | 1 |
| 0 | 0 | 1 | 1 | 1 | ↑ | Toggle |
Parameters
| Parameter | Description | Units | Default |
|---|---|---|---|
| IC | Output initial state. | LOW | |
| CLKTPLH | Delay from clock to out high. | s | DGTDELAY |
| CLKTPHL | Delay from clock to out low. | s | DGTDELAY |
| PRETPLH | Delay from preset to out high. | s | DGTDELAY |
| PRETPHL | Delay from preset to out low. | s | DGTDELAY |
| CLRTPLH | Delay from clear to out high. | s | DGTDELAY |
| CLRTPHL | Delay from clear to out low. | s | DGTDELAY |
| IN_MODE | Inputs mode. | IN | |
| OUT_MODE | Outputs mode. | OUT | |
| IOMODEL | The name of an I/O model, which describes the device’s loading and driving characteristics. | DGTDEFIOMODEL | |
| POWER_NODE | Digital power node name. Is the node used by the interface subcircuits which connect analog nodes to digital nodes. | $G_DPWR | |
| GROUND_NODE | Digital ground node name. Is the node used by the interface subcircuits which connect analog nodes to digital nodes. | $G_DGND |