Toggle Flip-Flop with Toggle and Clock Enable and Synchronous Reset and Set
When the synchronous reset input (R) is High, it overrides all other inputs and the data output (Q) is reset Low. When the synchronous set input (S) is High and R is Low, clock enable input (CE) is overridden and output Q is set High. (Reset has precedence over Set.) When toggle enable input (T) and CE are High and R and S are Low, output Q toggles, or changes state, during the Low-to-High clock transition.
Parameters
| Parameter | Description | Units | Default |
|---|---|---|---|
| IC | Output initial state. | LOW | |
| CLKTPLH | Delay from clock to out high. | s | DGTDELAY |
| CLKTPHL | Delay from clock to out low. | s | DGTDELAY |
| PRETPLH | Delay from set to out high. | s | DGTDELAY |
| PRETPHL | Delay from set to out low. | s | DGTDELAY |
| CLRTPLH | Delay from reset to out high. | s | DGTDELAY |
| CLRTPHL | Delay from reset to out low. | s | DGTDELAY |
| IN_MODE | Inputs mode. | IN | |
| OUT_MODE | Outputs mode. | OUT | |
| IOMODEL | The name of an I/O model, which describes the device’s loading and driving characteristics. | DGTDEFIOMODEL | |
| POWER_NODE | Digital power node name. Is the node used by the interface subcircuits which connect analog nodes to digital nodes. | $G_DPWR | |
| GROUND_NODE | Digital ground node name. Is the node used by the interface subcircuits which connect analog nodes to digital nodes. | $G_DGND |