4-Bit Serial-In Parallel-Out Shift Register with Clock Enable and Asynchronous Clear

SR4CE is a 4-bit shift register with a shift-left serial input (SLI), parallel outputs (Q3 – Q0), and clock enable (CE) and asynchronous clear (CLR) inputs. The CLR input, when High, overrides all other inputs and resets the data outputs (Q3 – Q0) Low. When CE is High and CLR is Low, the data on the SLI input is loaded into the first bit of the shift register during the Low-to-High clock (C) transition and appears on the Q0 output. During subsequent Low-to-High clock transitions, when CE is High and CLR is Low, data is shifted to the next highest bit position as new data is loaded into Q0 (SLI->Q0, Q0->Q1, Q1->Q2, and so forth). The register ignores clock transitions when CE is Low.

Registers can be cascaded by connecting the Q3 output of one stage to the SLI input of the next stage and connecting clock, CE, and CLR in parallel.

The default initial state of all flip-flops is zero.

Parameters