8-Bit Serial-In Parallel-Out Shift Register with Active-Low Asynchronous Clear

X74_165S is an 8-bit shift register with serial-input (SI), parallelinputs (H – A), parallel-outputs (QH – QA), and two control inputs – clock enable (CE) and active-Low shift/load enable (S_L). When S_L is Low, data on the H – A inputs is loaded into the corresponding QH – QA bits of the register on the Low-to-High clock (C) transition. When CE and S_L are High, data on the SI input is loaded into the first bit of the register during the Low-to-High clock transition. During subsequent Low-to-High clock transitions, with CE and S_L High, the data is shifted to the next-highest bit position (shift right) as new data is loaded into QA (SI->QA, QA->QB, QB->QC, and so forth). The register ignores clock transitions when CE is Low and S_L is High. The default initial state of all flip-flops is zero.

Registers can be cascaded by connecting the QH output of one stage to the SI input of the next stage and connecting clock, CE, and S_L inputs in parallel.

Parameters