| ADC |
Analog-to-Digital Converter
The ADC converts the analog voltage at input to an equivalent digital representation. If the analog voltage at input is less than voltage at Vref-, then all data bits are set to ZERO, and over-range is set to ONE. If the analog voltage at input exceeds the voltage at Vref+ then all data bits are set to ONE, and the over-range pin is set to ONE.
The sampling of the input voltage occurs on the rising edge of the CONVERT
signal. Only one conversion is performed per rising edge. The Output pins go
to the UNKNOWN state and the STATUS pin goes to the ONE state TPCS seconds
after the rising edge of the CONVERT signal. TPSD seconds later, the Output
pins change to valid data. TPDS seconds later, the STATUS pin goes to the
ZERO state.
This model also posts an input load value (in farads) based on the
parameter input_load.
| Description | Direction | Default Type | Allowed Types | Vector | Vector Bounds | Null Allowed |
| Input | IN | v | v,vd,i,id,vnam | NO | NO | |
| Vref- | IN | v | v,vd,i,id,vnam | NO | NO | |
| Vref+ | IN | v | v,vd,i,id,vnam | NO | NO | |
| Convert | IN | d | d | NO | NO | |
| Status | OUT | d | d | NO | NO | |
| Over-range | OUT | d | d | NO | NO | |
| Output | OUT | d | d | YES | 1 / - | NO |
| Name | Description | Data Type | Default Value | Limits | Vector | Null Allowed |
| tpcs | time delay from rising edge of convert to rising edge of status | Real | 1.0e-9 | 1e-12 / - | NO | YES |
| tpsd | time delay from rising edge of status to output and over-range signals | Real | 1.0e-9 | 1e-12 / - | NO | YES |
| tpds | time delay from output and over-range signals to falling edge of status | Real | 1.0e-9 | 1e-12 / - | NO | YES |
| input_load | capacitive input load (F) | Real | 1.0e-12 | NO | YES |
aadc1 1 2 3 4 5 6 [7 8 9 10] adcl
.model adcl adc(tpcs=1.0e-6 tpsd=1.0e-6 tpds=1.0e-6 input_load=5.Oe-12)