Frequency Divider

The digital frequency divider is a programmable step-down divider which accepts an arbitrary divisor (div_factor), a duty-cycle term (high_cycles), and an initial count value (i_count). The generated output is synchronized to the rising edges of the input signal. Rise delay and fall delay on the outputs may also be specified independently.

Port Table

Description Direction Default Type Allowed Types Vector Vector Bounds Null Allowed
frequency input IN d d NO   NO
frequency output OUT d d NO   NO

Parameter Table

Name Description Data Type Default Value Limits Vector Vector Bounds Null Allowed
div_factor divide factor Int 2 1 / - NO   YES
high_cycles number of high clock cycles Int 1 1 / - NO   YES
i_count output initial count value Int 0 0 / - NO   YES
rise_delay rise delay Real 1.0e-9 1e-12 / - NO   YES
fall_delay fall delay Real 1.0e-9 1e-12 / - NO   YES
freq_in_load freq_in load value (F) Real 1.0e-12   NO   YES


a4 3 7 divider
.model divider d_fdiv(div_factor = 5 high_cycles = 3 i_count = 4 rise_delay = 23e-9 fall_delay = 9e-9)

See also

XSPICE Devices
XSPICE Code Models