The digital RAM is an M-wide, N-deep random access memory element with programmable select lines, tristated data_out lines, and a single write/read line. The depth of the RAM (N) is set by the number of address lines input to the device. The value of N is related to the number of address input lines (P) by the following equation: 2p=N.

There is no reset line into the device. However, an initial value for all bits may be specified by setting the ic parameter to either 0 or 1. In reading a word from the ram, the read_delay value is invoked, and output will not appear until that delay has been satisfied. Separate rise and fall delays are not supported for this device.

Note that UNKNOWN inputs on the address lines are not allowed during a write. In the event that an address line does indeed go unknown during a write, THE ENTIRE CONTENTS OF THE RAM WILL BE SET TO UNKNOWN. This is in contrast to the data_in lines being set to unknown during a write; in that case, only the selected word will be corrupted, and this is corrected once the data lines settle back to a known value. Note that protection is added to the write_en line such that extended UNKNOWN values on that line are interpreted as ZERO values. This is the equivalent of a read operation and will not corrupt the contents of the RAM. A similar mechanism exists for the select lines. If they are unknown, then it is assumed that the chip is not selected.

Detailed timing-checking routines are not provided in this model, other than for the enable_delay and select_delay restrictions on read operations. You are advised, therefore, to carefully check the timing into and out of the RAM for correct read and write cycle times, setup and hold times, etc. for the particular device they arc attempting to model.

Port Table

Description Direction Default Type Allowed Types Vector Vector Bounds Null Allowed
data input line(s) IN d d YES 1 / - NO
data output line(s) OUT d d YES 1 / - NO
address input line(s) IN d d YES 1 / - NO
write enable IN d d NO   NO
chip select line(s) IN d d YES 1 / 16 NO

Parameter Table

Name Description Data Type Default Value Limits Vector Vector Bounds Null Allowed
select_value decimal active value for select line comparison Int 1 0 / 32767 NO   YES
ic initial bit state Int 2 0 / 2 NO   YES
read_delay read delay from address/select/write_en active Real 100.0e-9 1e-12 / - NO   YES
data_load data_in load value (F) Real 1.0e-12   NO   YES
address_load address line load value (F) Real 1.0e-12   NO   YES
select_load select load value (F) Real 1.0e-12   NO   YES
enable_load enable line load value (F) Real 1.0e-12   NO   YES


a4 [3 4 5 6] [3 4 5 6] [12 13 14 15 16 17 18 19] 30 [22 23 24] ram2 
.model ram2 d_ram(select_value = 2 ic = 2 read_delay = 80e-9)

See also

XSPICE Devices
XSPICE Code Models