| D_TFF |
Toggle Flip Flop
The digital toggle-type flip flop is a one-bit, edge-triggered storage element which will toggle its current state whenever the clk input line transitions from low to high (ZERO to ONE). In addition, set and reset signals exist, and each of the three methods of changing the stored output of the d_tff have separate load values and delays associated with them.
Note that in asynchronous mode any UNKNOWN input on the set or reset lines
immediately results in an UNKNOWN output.
| Description | Direction | Default Type | Allowed Types | Vector | Vector Bounds | Null Allowed |
| toggle input | IN | d | d | NO | NO | |
| clock | IN | d | d | NO | NO | |
| clock enable | IN | d | d | NO | YES | |
| data | IN | d | d | NO | YES | |
| load data | IN | d | d | NO | YES | |
| set | IN | d | d | NO | YES | |
| reset | IN | d | d | NO | YES | |
| data output | OUT | d | d | NO | YES | |
| inverted data output | OUT | d | d | NO | YES |
| Name | Description | Data Type | Default Value | Limits | Vector | Vector Bounds | Null Allowed |
| DELAY | generic delay | Real | 1.0e-9 | 1e-12 / - | NO | YES | |
| CLKTPLH | delay from clock to out high | Real | 0 | 1e-12 / - | NO | YES | |
| CLKTPHL | delay from clock to out low | Real | 0 | 1e-12 / - | NO | YES | |
| PRETPLH | delay from set to out high | Real | 0 | 1e-12 / - | NO | YES | |
| PRETPHL | delay from set to out low | Real | 0 | 1e-12 / - | NO | YES | |
| CLRTPLH | delay from reset to out high | Real | 0 | 1e-12 / - | NO | YES | |
| CLRTPHL | delay from reset to out low | Real | 0 | 1e-12 / - | NO | YES | |
| IC | output initial state (0=low, 1=high, 2=unknown) | Int | 0 | 0 / 2 | NO | YES | |
| T_LOAD | toggle load value (F) | Real | 1.0e-12 | NO | YES | ||
| CLK_LOAD | clk load value (F) | Real | 1.0e-12 | NO | YES | ||
| SET_LOAD | set load value (F) | Real | 1.0e-12 | NO | YES | ||
| RESET_LOAD | reset load value (F) | Real | 1.0e-12 | NO | YES | ||
| DATA_LOAD | data load value (F) | Real | 1.0e-12 | NO | YES | ||
| LOADDATA_LOAD | loaddata load value (F) | Real | 1.0e-12 | NO | YES | ||
| CLKENABLE_LOAD | clock enable load value (F) | Real | 1.0e-12 | NO | YES | ||
| MODE | 0=asynchronous Set and Reset. 1=synchronous mode. Reset has precedence over Set. 3=synchronous mode. Set has precedence over Reset. |
Int | 0 | NO | YES |
a8 1 2 3 4 5 6 7 8 9 flop3
.model flop3 d_tff(delay=13e-9)