Tristate

The digital tristate is a simple tristate gate. The state seen on the input line is reflected in the output. The state seen on the enable line determines the strength of the output. Thus, a ONE forces the output to its state with a STRONG strength. A ZERO forces the output to go to a HI_IMPEDANCE strength. The model posts input and enable load values (in farads) based on the parameters input_load and enable. The output of this model does NOT, however, respond to the total loading it sees on its output; it will always drive the output with the specified delay. Note also that to maintain the technology-independence of the model, any UNKNOWN input, or any floating input causes the output to also go UNKNOWN. Likewise, any UNKNOWN input on the enable line causes the output to go to an UNDETERMINED strength value.

Port Table

Description Direction Default Type Allowed Types Vector Vector Bounds Null Allowed
Input IN d d NO   NO
Enable IN d d NO   NO
Output OUT d d NO   NO

Parameter Table

Name Description Data Type Default Value Limits Vector Vector Bounds Null Allowed
delay Generic propagation delay Real 1.0e-9 1.0e-12 / - NO   YES
TPLH Propagation delay from ZERO to ONE Real   1.0e-12 / - NO   YES
TPHL Propagation delay from ONE to ZERO Real   1.0e-12 / - NO   YES
TPZH Propagation delay from HI_IMPEDANCE to ONE Real   1.0e-12 / - NO   YES
TPZL Propagation delay from HI_IMPEDANCE to ZERO Real   1.0e-12 / - NO   YES
TPHZ Propagation delay from ONE to HI_IMPEDANCE Real   1.0e-12 / - NO   YES
TPLZ Propagation delay from ZERO to HI_IMPEDANCE Real   1.0e-12 / - NO   YES
input_load input load value (F) Real 1.0e-12   NO   YES
enable_load enable load value (F) Real 1.0e-12   NO   YES

Example

a9 1 2 8 tri7
  
.model tri7 d_tristate(delay = 0.5e-9 input_load = 0.5e-12 enable_load = 0.5e-12)

See also

XSPICE Devices
XSPICE Code Models